/*****************************************************************************
 *   Copyright(C)2009-2022 by VSF Team                                       *
 *                                                                           *
 *  Licensed under the Apache License, Version 2.0 (the "License");          *
 *  you may not use this file except in compliance with the License.         *
 *  You may obtain a copy of the License at                                  *
 *                                                                           *
 *     http://www.apache.org/licenses/LICENSE-2.0                            *
 *                                                                           *
 *  Unless required by applicable law or agreed to in writing, software      *
 *  distributed under the License is distributed on an "AS IS" BASIS,        *
 *  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *
 *  See the License for the specific language governing permissions and      *
 *  limitations under the License.                                           *
 *                                                                           *
 ****************************************************************************/

#ifndef __HAL_DRIVER_HME_H7_DMA_H__
#define __HAL_DRIVER_HME_H7_DMA_H__

/*============================ INCLUDES ======================================*/

#include "hal/vsf_hal_cfg.h"

#if VSF_HAL_USE_DMA == ENABLED

#include "../../__device.h"

#ifdef __cplusplus
extern "C" {
#endif

/*============================ MACROS ========================================*/

#define VSF_DMA_CFG_REIMPLEMENT_TYPE_CHANNEL_MODE   ENABLED

/*============================ MACROFIED FUNCTIONS ===========================*/
/*============================ TYPES =========================================*/

typedef enum vsf_dma_channel_mode_t {
    VSF_DMA_SRC_WIDTH_BYTE_1         = (0x00 << 1),
    VSF_DMA_SRC_WIDTH_BYTES_2        = (0x01 << 1),
    VSF_DMA_SRC_WIDTH_BYTES_4        = (0x02 << 1),
    VSF_DMA_SRC_WIDTH_BYTES_8        = (0x03 << 1),
    VSF_DMA_SRC_WIDTH_BYTES_16       = (0x04 << 1),
    VSF_DMA_SRC_WIDTH_BYTES_32       = (0x05 << 1),

    VSF_DMA_DST_WIDTH_BYTE_1         = (0x00 << 4),
    VSF_DMA_DST_WIDTH_BYTES_2        = (0x01 << 4),
    VSF_DMA_DST_WIDTH_BYTES_4        = (0x02 << 4),
    VSF_DMA_DST_WIDTH_BYTES_8        = (0x03 << 4),
    VSF_DMA_DST_WIDTH_BYTES_16       = (0x04 << 4),
    VSF_DMA_DST_WIDTH_BYTES_32       = (0x05 << 4),

    VSF_DMA_DST_ADDR_INCREMENT       = (0x00 << 7),
    VSF_DMA_DST_ADDR_DECREMENT       = (0x01 << 7),
    VSF_DMA_DST_ADDR_NO_CHANGE       = (0x02 << 7),

    VSF_DMA_SRC_ADDR_INCREMENT       = (0x00 << 9),
    VSF_DMA_SRC_ADDR_DECREMENT       = (0x01 << 9),
    VSF_DMA_SRC_ADDR_NO_CHANGE       = (0x02 << 9),

    VSF_DMA_DST_BURST_LENGTH_1       = (0x00 << 11),
    VSF_DMA_DST_BURST_LENGTH_4       = (0x01 << 11),
    VSF_DMA_DST_BURST_LENGTH_8       = (0x02 << 11),
    VSF_DMA_DST_BURST_LENGTH_16      = (0x03 << 11),
    VSF_DMA_DST_BURST_LENGTH_32      = (0x04 << 11),
    VSF_DMA_DST_BURST_LENGTH_64      = (0x05 << 11),
    VSF_DMA_DST_BURST_LENGTH_128     = (0x06 << 11),
    VSF_DMA_DST_BURST_LENGTH_256     = (0x05 << 11),

    VSF_DMA_SRC_BURST_LENGTH_1       = (0x00 << 14),
    VSF_DMA_SRC_BURST_LENGTH_4       = (0x01 << 14),
    VSF_DMA_SRC_BURST_LENGTH_8       = (0x02 << 14),
    VSF_DMA_SRC_BURST_LENGTH_16      = (0x03 << 14),
    VSF_DMA_SRC_BURST_LENGTH_32      = (0x04 << 14),
    VSF_DMA_SRC_BURST_LENGTH_64      = (0x05 << 14),
    VSF_DMA_SRC_BURST_LENGTH_128     = (0x06 << 14),
    VSF_DMA_SRC_BURST_LENGTH_256     = (0x07 << 14),

    VSF_DMA_MEMORY_TO_MEMORY         = (0x00 << 20),
    VSF_DMA_MEMORY_TO_PERIPHERAL     = (0x01 << 20),
    VSF_DMA_PERIPHERA_TO_MEMORY      = (0x02 << 20),
    VSF_DMA_PERIPHERA_TO_PERIPHERAL  = (0x03 << 20),


    VSF_DMA_PERIPHERA_TO_MEMORY_FLOW_BY_SOURCE
                                     = (0x04 << 20),
    VSF_DMA_PERIPHERA_TO_PERIPHERAL_FLOW_BY_SOURCE
                                     = (0x05 << 20),
    VSF_DMA_MEMORY_TO_PERIPHERAL_FLOW_BY_PERIPH
                                     = (0x06 << 20),
    VSF_DMA_PERIPHERA_TO_PERIPHERAL_FLOW_BY_DEST
                                     = (0x07 << 20),

    HW_DMA_MODE_ALL_BITS_MASK        = (0x07ul <<  1) | (0x07ul <<  4) | (0x03ul <<  7) | (0x03ul << 19) |
                                       (0x07ul << 11) | (0x07ul << 14) | (0x07ul << 20),

    VSF_DMA_DST_BURST_LENGTH_2       = (0x01 << 24),
    VSF_DMA_SRC_BURST_LENGTH_2       = (0x01 << 25),


    VSF_DMA_PRIOPIRY_LOW             = (0x00 << 26),
    VSF_DMA_PRIOPIRY_MIDIUM          = (0x01 << 26),
    VSF_DMA_PRIOPIRY_HIGH            = (0x02 << 26),
    VSF_DMA_PRIOPIRY_VERY_HIGH       = (0x03 << 26),

    // request line
} vsf_dma_channel_mode_t;

typedef enum vsf_hw_dma_chn_no_t {
    VSF_HW_DMA_I2C0_TX  = 0,
    VSF_HW_DMA_I2C0_RX  = 1,
    VSF_HW_DMA_I2C1_TX  = 2,
    VSF_HW_DMA_I2C1_RX  = 3,
    VSF_HW_DMA_I2C2_TX  = 4,
    VSF_HW_DMA_I2C2_RX  = 5,

    VSF_HW_DMA_UART0_TX = 6,
    VSF_HW_DMA_UART0_RX = 7,
    VSF_HW_DMA_UART1_TX = 8,
    VSF_HW_DMA_UART1_RX = 9,

    VSF_HW_DMA_SPI0_TX  = 10,
    VSF_HW_DMA_SPI0_RX  = 11,
    VSF_HW_DMA_SPI1_TX  = 12,
    VSF_HW_DMA_SPI1_RX  = 13,
    VSF_HW_DMA_SPI3_TX  = 14,
    VSF_HW_DMA_SPI3_RX  = 15,

    // unsupported dma
    VSF_HW_DMA_UART2_TX = -1,
    VSF_HW_DMA_UART2_RX = -1,
    VSF_HW_DMA_SPI2_TX  = -1,
    VSF_HW_DMA_SPI2_RX  = -1,
} vsf_hw_dma_chn_no_t;

/*============================ INCLUDES ======================================*/


#ifdef __cplusplus
}
#endif

#endif      // VSF_HAL_USE_DMA
#endif      // __HAL_DRIVER_HME_H7_DMA_H__
/* EOF */
